// SPDX-FileCopyrightText: © 2025 Tenstorrent AI ULC
//
// SPDX-License-Identifier: Apache-2.0

#ifndef __OVERLAY_ADDRESSES_HPP__
#define __OVERLAY_ADDRESSES_HPP__

#include <tt_tensix_noc_overlay_reg.h>
#include <overlay_reg.h>
#include <noc_config_reg.h>

#define MEM_PORT_CACHEABLE_BASE_ADDR (uint64_t)MEMORY_PORT_CACHEABLE_MEM_PORT_MEM_BASE_ADDR
#define MEM_PORT_NONCACHEABLE_BASE_ADDR (uint64_t)MEMORY_PORT_NONCACHEABLE_MEM_PORT_MEM_BASE_ADDR
#define PERIPH_PORT_BASE_ADDR (uint64_t)TT_CLUSTER_CTRL_REG_MAP_BASE_ADDR
#define GLOBAL_CMD_BUF_CFG_BASE_ADDR (uint64_t)TT_GLOBAL_CMD_BUF_CFG_REG_MAP_BASE_ADDR
#define GLOBAL_CMD_BUF_BASE_ADDR (uint64_t)TT_GLOBAL_CMD_BUF_REG_MAP_BASE_ADDR
#define L2_FLUSH_ADDR (uint64_t)TT_CACHE_CONTROLLER_FLUSH64_REG_ADDR
#define L2_INVALIDATE_ADDR (uint64_t)TT_CACHE_CONTROLLER_INVALIDATE64_REG_ADDR
#define L2_FULL_INVALIDATE_ADDR (uint64_t)TT_CACHE_CONTROLLER_FULLINVALIDATE_REG_ADDR

#define WRITE_REG32(addr, val) ((*((volatile uint32_t*)(addr))) = (val))
#define READ_REG32(addr) (*((volatile uint32_t*)(addr)))

#define WRITE_REG64(addr, val) ((*((volatile uint64_t*)(addr))) = (val))
#define READ_REG64(addr) (*((volatile uint64_t*)(addr)))

#define WRITE_MEM_PORT(offset, val) ((*((volatile uint64_t*)((MEM_PORT_CACHEABLE_BASE_ADDR + offset)))) = (val))
#define READ_MEM_PORT(offset) (*((volatile uint64_t*)((MEM_PORT_CACHEABLE_BASE_ADDR + offset))))

#define WRITE_PERIPH_PORT32(offset, val) ((*((volatile uint32_t*)((PERIPH_PORT_BASE_ADDR + offset)))) = (val))
#define READ_PERIPH_PORT32(offset) (*((volatile uint32_t*)((PERIPH_PORT_BASE_ADDR + offset))))

#define WRITE_PERIPH_PORT64(offset, val) ((*((volatile uint64_t*)((PERIPH_PORT_BASE_ADDR + offset)))) = (val))
#define READ_PERIPH_PORT64(offset) (*((volatile uint64_t*)((PERIPH_PORT_BASE_ADDR + offset))))

#define WRITE_GLOBAL_CMD_BUF_CFG_PORT32(offset, val) \
    ((*((volatile uint32_t*)((GLOBAL_CMD_BUF_CFG_BASE_ADDR + offset)))) = (val))
#define READ_GLOBAL_CMD_BUF_CFG_PORT32(offset) (*((volatile uint32_t*)((GLOBAL_CMD_BUF_CFG_BASE_ADDR + offset))))

#define WRITE_GLOBAL_CMD_BUF_CFG_PORT64(offset, val) \
    ((*((volatile uint64_t*)((GLOBAL_CMD_BUF_CFG_BASE_ADDR + offset)))) = (val))
#define READ_GLOBAL_CMD_BUF_CFG_PORT64(offset) (*((volatile uint64_t*)((GLOBAL_CMD_BUF_CFG_BASE_ADDR + offset))))

#define WRITE_GLOBAL_CMD_BUF_PORT32(offset, val) \
    ((*((volatile uint32_t*)((GLOBAL_CMD_BUF_BASE_ADDR + offset)))) = (val))
#define READ_GLOBAL_CMD_BUF_PORT32(offset) (*((volatile uint32_t*)((GLOBAL_CMD_BUF_BASE_ADDR + offset))))

#define WRITE_GLOBAL_CMD_BUF_PORT64(offset, val) \
    ((*((volatile uint64_t*)((GLOBAL_CMD_BUF_BASE_ADDR + offset)))) = (val))
#define READ_GLOBAL_CMD_BUF_PORT64(offset) (*((volatile uint64_t*)((GLOBAL_CMD_BUF_BASE_ADDR + offset))))

#define WRITE_POSTCODE(mhartid, postcode) (WRITE_PERIPH_PORT32(C0_POSTCODE + (0x8 * mhartid), postcode))
#define WRITE_SCRATCH(num, val) (WRITE_PERIPH_PORT32(SCRATCH_0_OFFSET + (0x8 * num), val))
// ------------------------------------------------
//  Register space address map
// ------------------------------------------------

#define CORE_0_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_0__REG_OFFSET
#define CORE_1_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_1__REG_OFFSET
#define CORE_2_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_2__REG_OFFSET
#define CORE_3_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_3__REG_OFFSET
#define CORE_4_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_4__REG_OFFSET
#define CORE_5_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_5__REG_OFFSET
#define CORE_6_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_6__REG_OFFSET
#define CORE_7_RESET_VECTOR TT_CLUSTER_CTRL_RESET_VECTOR_7__REG_OFFSET

#define SCRATCH_0_OFFSET TT_CLUSTER_CTRL_SCRATCH_0__REG_OFFSET
#define SCRATCH_1_OFFSET TT_CLUSTER_CTRL_SCRATCH_1__REG_OFFSET
#define SCRATCH_2_OFFSET TT_CLUSTER_CTRL_SCRATCH_2__REG_OFFSET
#define SCRATCH_3_OFFSET TT_CLUSTER_CTRL_SCRATCH_3__REG_OFFSET
#define SCRATCH_4_OFFSET TT_CLUSTER_CTRL_SCRATCH_4__REG_OFFSET
#define SCRATCH_5_OFFSET TT_CLUSTER_CTRL_SCRATCH_5__REG_OFFSET
#define SCRATCH_6_OFFSET TT_CLUSTER_CTRL_SCRATCH_6__REG_OFFSET
#define SCRATCH_7_OFFSET TT_CLUSTER_CTRL_SCRATCH_7__REG_OFFSET
#define SCRATCH_8_OFFSET TT_CLUSTER_CTRL_SCRATCH_8__REG_OFFSET
#define SCRATCH_9_OFFSET TT_CLUSTER_CTRL_SCRATCH_9__REG_OFFSET
#define SCRATCH_10_OFFSET TT_CLUSTER_CTRL_SCRATCH_10__REG_OFFSET
#define SCRATCH_11_OFFSET TT_CLUSTER_CTRL_SCRATCH_11__REG_OFFSET
#define SCRATCH_12_OFFSET TT_CLUSTER_CTRL_SCRATCH_12__REG_OFFSET
#define SCRATCH_13_OFFSET TT_CLUSTER_CTRL_SCRATCH_13__REG_OFFSET
#define SCRATCH_14_OFFSET TT_CLUSTER_CTRL_SCRATCH_14__REG_OFFSET
#define SCRATCH_15_OFFSET TT_CLUSTER_CTRL_SCRATCH_15__REG_OFFSET
#define SCRATCH_16_OFFSET TT_CLUSTER_CTRL_SCRATCH_16__REG_OFFSET
#define SCRATCH_17_OFFSET TT_CLUSTER_CTRL_SCRATCH_17__REG_OFFSET
#define SCRATCH_18_OFFSET TT_CLUSTER_CTRL_SCRATCH_18__REG_OFFSET
#define SCRATCH_19_OFFSET TT_CLUSTER_CTRL_SCRATCH_19__REG_OFFSET
#define SCRATCH_20_OFFSET TT_CLUSTER_CTRL_SCRATCH_20__REG_OFFSET
#define SCRATCH_21_OFFSET TT_CLUSTER_CTRL_SCRATCH_21__REG_OFFSET
#define SCRATCH_22_OFFSET TT_CLUSTER_CTRL_SCRATCH_22__REG_OFFSET
#define SCRATCH_23_OFFSET TT_CLUSTER_CTRL_SCRATCH_23__REG_OFFSET

// ------------------------------------------------
//  Register defines
// ------------------------------------------------

#define C0_POSTCODE SCRATCH_0_OFFSET
#define C0_SCRATCH SCRATCH_1_OFFSET
#define C1_POSTCODE SCRATCH_2_OFFSET
#define C1_SCRATCH SCRATCH_3_OFFSET
#define C2_POSTCODE SCRATCH_4_OFFSET
#define C2_SCRATCH SCRATCH_5_OFFSET
#define C3_POSTCODE SCRATCH_6_OFFSET
#define C3_SCRATCH SCRATCH_7_OFFSET
#define C4_POSTCODE SCRATCH_8_OFFSET
#define C4_SCRATCH SCRATCH_9_OFFSET
#define C5_POSTCODE SCRATCH_10_OFFSET
#define C5_SCRATCH SCRATCH_11_OFFSET
#define C6_POSTCODE SCRATCH_12_OFFSET
#define C6_SCRATCH SCRATCH_13_OFFSET
#define C7_POSTCODE SCRATCH_14_OFFSET
#define C7_SCRATCH SCRATCH_15_OFFSET

#define C0_TEST_TSTAMP C0_SCRATCH
#define C1_TEST_TSTAMP C1_SCRATCH
#define C2_TEST_TSTAMP C2_SCRATCH
#define C3_TEST_TSTAMP C3_SCRATCH
#define C4_TEST_TSTAMP C4_SCRATCH
#define C5_TEST_TSTAMP C5_SCRATCH
#define C6_TEST_TSTAMP C6_SCRATCH
#define C7_TEST_TSTAMP C7_SCRATCH

#define POSTCODE_FAIL (0xdeadbeef)
#define POSTCODE_PASS (0xfaaccaa5)

#define INIT_SEED_ADDR SCRATCH_19_OFFSET
#define STIM_GEN_ADDR SCRATCH_21_OFFSET
#define STIM_CHECK_ADDR SCRATCH_22_OFFSET
#define STIM_CHECK_SEQ_ID_ADDR SCRATCH_23_OFFSET

#endif  // __OVERLAY_ADDRESSES_HPP__
